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19-5450; Rev 0; 7/10
3.3V, 8Mb, Nonvolatile SRAM with Clock
General Description
The DS3065WP consists of a static RAM, a nonvolatile (NV) controller, and a real-time clock (RTC). These components are packaged on a surface-mount substrate and require post-assembly attachment of a DS9034IPCX+ battery cap. Whenever VCC is applied to the module, it powers the clock and SRAM from the external power source, and allows the contents of the clock registers or SRAM to be modified. When VCC is powered down or out of tolerance, the controller write protects the memory contents and powers the clock and SRAM from the battery.
S Integrated RTC S Unconditionally Write Protects the Clock and
Features
S Reflowable, 34-Pin PowerCap Package
DS3065WP
SRAM When VCC is Out of Tolerance
S Automatically Switches to Battery Supply When
VCC Power Failures Occur
S Extended Industrial Temperature Range (-40NC to
+85NC)
S Underwriters Laboratories Recognized
Applications
RAID Systems and Servers/Gaming POS Terminals/Fire Alarms Industrial Controllers/PLCs Data-Acquisition Systems Routers/Switches
Ordering Information
PART DS3065WP-100IND+ TEMP RANGE -40NC to +85NC SPEED (ns) 100 SUPPLY VOLTAGE (V) 3.3 Q0.3 PIN-PACKAGE 34 PowerCap Module
Typical Operating Circuit
CE WR RD CS
MICROPROCESSOR OR DSP
CE WE OE CS DS3065WP 1024k x 8 NV SRAM AND RTC 8 BITS DQ0-DQ7
DATA
ADDRESS
20 BITS
A0-A19
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
3.3V, 8Mb, Nonvolatile SRAM with Clock DS3065WP
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground ....-0.3V to +4.6V Operating Temperature Range .......................... -40NC to +85NC Storage Temperature Range............................ -55NC to +125NC Lead Temperature (soldering, 10s) ................................+260NC (intended for minor rework/touchup purposes only) Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1) PARAMETER Supply Voltage Logic 1 Input Logic 0 Input SYMBOL VCC VIH VIL CONDITIONS MIN 3.0 2.2 0.0 TYP 3.3 MAX 3.6 VCC 0.4 UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V Q0.3V, TA = -40NC to +85NC, unless otherwise noted.) PARAMETER Input Leakage Current I/O Leakage Current Output-Current High Output-Current Low Standby Current Operating Current Write-Protection Voltage SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 VTP VCE = VCS = VCC VOH = 2.4V VOL = 0.4V VCE = VCS = 2.2V VCE = VCS = VCC - 0.2V tRC = 200ns, outputs open 2.8 2.9 CONDITIONS MIN -1.0 -1.0 -1.0 2.0 0.6 0.6 2.0 1.5 50 3.0 TYP MAX +1.0 +1.0 UNITS FA FA mA mA mA mA V
PIN CAPACITANCE
(TA = +25NC, unless otherwise noted.) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN COUT CONDITIONS Not production tested Not production tested MIN TYP 15 15 MAX UNITS pF pF
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V Q0.3V, TA = -40NC to +85NC, unless otherwise noted.) PARAMETER Read Cycle Time Access Time OE to Output Valid RTC OE to Output Valid CE or CS to Output Valid OE or CE or CS to Output Active 2 SYMBOL tRC tACC tOE tOEC tCO tCOE (Note 2) 5 CONDITIONS MIN 100 100 50 60 100 TYP MAX UNITS ns ns ns ns ns ns
3.3V, 8Mb, Nonvolatile SRAM with Clock
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.3V Q0.3V, TA = -40NC to +85NC, unless otherwise noted.) PARAMETER Output High Impedance from Deselection Output Hold from Address Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Impedance from WE Output Active from WE Data Setup Time Data Hold Time Chip-to-Chip Setup Time SYMBOL tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 tCCS (Note 4) (Note 5) (Note 2) (Note 2) (Note 6) (Note 4) (Note 5) 5 40 0 20 40 (Note 3) (Note 2) 5 100 75 0 5 20 40 CONDITIONS MIN TYP MAX 40 UNITS ns ns ns ns ns ns ns ns ns ns ns
DS3065WP
POWER-DOWN/POWER-UP TIMING
(TA = -40NC to +85NC, unless otherwise noted.) PARAMETER VCC Fail Detect to CE, CS, and WE Inactive Time VCC Slew from VTP to 0V VCC Slew from 0V to VTP VCC Valid to CE, CS, and WE Inactive VCC Valid to End of Write Protection SYMBOL tPD tF tR tPU tREC (Note 7) 150 150 2 125 CONDITIONS MIN TYP MAX 1.5 UNITS Fs Fs Fs ms ms
DATA RETENTION
(TA = +25NC, unless otherwise noted.) PARAMETER Expected Data-Retention Time SYMBOL tDR (Notes 7, 8) CONDITIONS MIN 10 TYP MAX UNITS Years
AC TEST CONDITIONS
Voltage Range on Any Pin Relative to Ground: -0.3V to +4.6V Input Pulse Levels: VIL = 0V, VIH = 2.7V Input Pulse Rise and Fall Times: 5ns Input and Output Timing Reference Level: 1.5V Output Load: 1 TTL Gate + CL (100pF) including scope and jig
3
3.3V, 8Mb, Nonvolatile SRAM with Clock DS3065WP
Read Cycle
tRC ADDRESSES VIH VIL VIH VIL tOH VIH VIL tCO tOEC tOE VIL tCOE tCOE DOUT VOH VOL OUTPUT DATA VALID tOD VOH VOL tOD VIH VIH VIL
CE OR CS
VIH
tACC
VIH OE
(SEE NOTE 9.)
Write Cycle 1
tWC ADDRESSES VIH VIL tAW VIL tWP VIH tODW DOUT HIGH IMPEDANCE tDS VIH DIN (SEE NOTES 2, 3, 4, 6, 10-13.) VIL DATA IN STABLE tDH1 VIH VIL VIL VIL VIH tOEW VIL tWR1 VIH VIL VIH VIL
CE OR CS WE
4
3.3V, 8Mb, Nonvolatile SRAM with Clock
Write Cycle 2
tWC VIH VIL tAW CE OR CS WE tCOE VIH VIL VIL VIL VIH VIL tODW VIL tWP VIH tWR2 VIH VIL VIH VIL
DS3065WP
ADDRESSES
DOUT tDS VIH DIN VIL (SEE NOTES 2, 3, 5, 6, 10-13.) DATA IN STABLE VIL tDH2 VIH
Power-Down/Power-Up Condition
VCC VTP tDR
~2.5V
tF tPD CE, WE AND CS BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY (SEE NOTES 1, 7.) tPU VIH tR tREC SLEWS WITH VCC
5
3.3V, 8Mb, Nonvolatile SRAM with Clock
Note 1: All voltages are referenced to ground. Note 2: These parameters are sampled with a 5pF load and are not 100% tested. Note 3: tWP is specified as the logical AND of CE with WE for SRAM writes, or CS with WE for RTC writes. tWP is measured from the later of the two related edges going low to the earlier of the two related edges going high. Note 4: tWR1 and tDH1 are measured from WE going high. Note 5: tWR2 and tDH2 are measured from CE going high for SRAM writes or CS going high for RTC writes. Note 6: tDS is measured from the earlier of CE or WE going high for SRAM writes, or from the earlier of CS or WE going high for RTC writes. Note 7: In a power-down condition, the voltage on any pin cannot exceed the voltage on VCC. Note 8: The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. Minimum expected data-retention time is based upon a single convection reflow exposure, followed by an attachment of a new DS9034I-PCX+. This parameter is assured by component selection, process control, and design. It is not measured directly during production testing. Note 9: WE is high for any read cycle. Note 10: VOE = VIH or VIL. If VOE = VIH during write cycle, the output buffers remain in a high-impedance state. Note 11: If the CE or CS low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high-impedance state during this period. Note 12: If the CE or CS high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the related CE or CS low transition, the output buffers remain in a high-impedance state during this period.
DS3065WP
6
3.3V, 8Mb, Nonvolatile SRAM with Clock
Typical Operating Characteristics
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
POWER-SUPPLY CURRENT vs. POWER-SUPPLY VOLTAGE
DS3065WP toc01
DS3065WP
POWER-SUPPLY CURRENT vs. POWER-SUPPLY VOLTAGE
VCE = VCS = VCC TA = +25C
DS3065WP toc02
8 7 SUPPLY CURRENT (mA) 6 5 4 3 2 1 0 3.0
5MHz CE-ACTIVATED 50% DUTY CYCLE 5MHz ADDRESS-ACTIVATED 100% DUTY CYCLE 1MHz CE-ACTIVATED 50% DUTY CYCLE
800 700 SUPPLY CURRENT (A) 600 500 400
1MHz ADDRESS-ACTIVATED 100% DUTY CYCLE
3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
300 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V)
SRAM OUTPUT-VOLTAGE HIGH vs. OUTPUT CURRENT
DS3065WP toc03
SRAM OUTPUT-VOLTAGE LOW vs. OUTPUT CURRENT
VCC = +3.0V, TA = +25C
DS3065WP toc04
4.0 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 -5
VCC = +3.0V, TA = +25C
0.4
OUTPUT VOLTAGE (V) -4 -3 -2 -1
0.3
0.2
0.1
0 0 0 1 2 3 4 5 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)
RTC OUTPUT-VOLTAGE HIGH vs. OUTPUT CURRENT
DS3065WP toc05
RTC OUTPUT-VOLTAGE LOW vs. OUTPUT CURRENT
VCC = +3.0V, TA = +25C
DS3065WP toc06
4.0 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 -5
VCC = +3.0V, TA = +25C
0.4
OUTPUT VOLTAGE (V) -4 -3 -2 -1
0.3
0.2
0.1
0 0 0 1 2 3 4 5 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)
7
3.3V, 8Mb, Nonvolatile SRAM with Clock DS3065WP
Pin Configuration
TOP VIEW
A19 A15 A16 CS VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X1 GND BAT X2
34
A18 A17 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
+
33 32 31 30
DS3065WP
29 28 27 26 25 24 23 22 21 20 19 18
PowerCap MODULE
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 8 NAME A19 A15 A16 CS VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND FUNCTION Address Input 19 Address Input 15 Address Input 16 Active-Low RTC Chip-Select Input Supply Voltage Active-Low Write-Enable Input Active-Low Output-Enable Input Active-Low SRAM Chip-Enable Input Data Input/Output 7 Data Input/Output 6 Data Input/Output 5 Data Input/Output 4 Data Input/Output 3 Data Input/Output 2 Data Input/Output 1 Data Input/Output 0 Ground PIN 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 NAME A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A17 A18 FUNCTION Address Input 0 Address Input 1 Address Input 2 Address Input 3 Address Input 4 Address Input 5 Address Input 6 Address Input 7 Address Input 8 Address Input 9 Address Input 10 Address Input 11 Address Input 12 Address Input 13 Address Input 14 Address Input 17 Address Input 18
3.3V, 8Mb, Nonvolatile SRAM with Clock
Functional Diagram
DS3065WP
DS9034I-PCX+
32.768kHz
CS
CS A0-A3 WE OE REAL-TIME CLOCK
CE VTP REF DELAY TIMING CIRCUITRY
UNINTERRUPTED POWER SUPPLY FOR THE SRAM AND RTC
VCC
VCC CE VSW REF OE WE SRAM DQ0-DQ7
REDUNDANT LOGIC
GND
CURRENT-LIMITING RESISTOR
REDUNDANT SERIES FET DS3065WP
BATTERY PROTECTION CIRCUITRY (UL RECOGNIZED) OE WE A0-A19
9
3.3V, 8Mb, Nonvolatile SRAM with Clock DS3065WP
Detailed Description
The DS3065WP is an 8Mb (1024k x 8 bits), fully static, nonvolatile (NV) memory similar in function and organization to the DS1265W NV SRAM, but containing an RTC. The device NV SRAM constantly monitors VCC for an outof-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit to the number of write cycles that can be executed, and no additional support circuitry is required for microprocessor interfacing. This device can be used in place of SRAM, EEPROM, or flash components. User access to either the SRAM or the RTC registers is accomplished with a byte-wide interface and discrete control inputs, allowing for a direct interface to many 3.3V microprocessor devices. The RTC contains a full-function clock/calendar with an RTC alarm, battery monitor, and power monitor. RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in a 24-hour BCD format. Corrections for day of the month and leap year are made automatically. The RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is on, the internal registers are continually updated, regardless of the state of the external registers, assuring that accurate RTC information is always maintained. The device constantly monitors the voltage of the internal battery. The battery-low flag (BLF) in the RTC FLAGS register is not writable and should always be a 0 when read. Should a 1 ever be present, the battery voltage is below ~ 2V and the contents of the clock and SRAM are questionable. The device module is constructed on a standard 34-pin PowerCap substrate. The device executes an SRAM read cycle whenever CS (RTC chip select) and WE (write enable) are inactive (high) and CE (SRAM chip enable) is active (low). The unique address specified by the 20 address inputs (A0-A19) defines which of the 1,048,576 bytes of SRAM data is to be accessed. Valid data is available to the eight data-output drivers within tACC (access time) after the last address input signal is stable, provided that CE and OE (output enable) access times are also satisfied. If CE and OE access times are not satisfied, data access must be measured from the later occurring signal (CE or OE), and the limiting parameter is either tCO for CE or tOE for OE rather than address access. The device executes an SRAM write cycle whenever CS is inactive (high) and the CE and WE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The CS and OE control signal should be kept inactive (high) during SRAM write cycles to avoid bus contention. However, if the output drivers have been enabled (CE and OE active), WE disables the outputs in tODW from its falling edge.
SRAM Read Mode
SRAM Write Mode
Table 1. RTC/Memory Operational Truth Table
CS 0 0 0 1 1 1 1 0 X = Don't care. 10 WE 1 1 0 1 1 0 X X CE 1 1 1 0 0 0 1 0 OE 0 1 X 0 1 X X X MODE RTC Read RTC Read RTC Write SRAM Read SRAM Read SRAM Write Standby Invalid (see Figure 2) ICC Active Active Active Active Active Active Standby Active OUTPUTS Active High Impedance High Impedance Active High Impedance High Impedance High Impedance Invalid
3.3V, 8Mb, Nonvolatile SRAM with Clock
Clock Operations
The device executes an RTC read cycle whenever CE (SRAM chip enable) and WE (write enable) are inactive (high) and CS (RTC chip select) is active (low). The least significant four address inputs (A0-A3) define which of the 16 RTC registers is to be accessed (see Table 3). Valid data is available to the eight data-output drivers within tACC (access time) after the last address input signal is stable, provided that CS and OE (output enable) access times are also satisfied. If CS and OE access times are not satisfied, data access must be measured from the later-occurring signal (CS or OE) and the limiting parameter is either tCO for CS or tOEC for OE rather than address access. The device executes an RTC write cycle whenever CE is inactive (high) and the CS and WE signals are active (low) after address inputs are stable. The later-occurring falling edge of CS or WE determines the start of the write cycle. The write cycle is terminated by the earlier rising edge of CS or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The CE and OE control signals should be kept inactive (high) during RTC write cycles to avoid bus contention. However, if the output drivers have been enabled (CS and OE active), WE disables the outputs in tODW from its falling edge. The oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB of the SECONDS register (B7 of F9h). Setting OSC to 1 stops the oscillator; setting OSC to 0 starts the oscillator. The initial state of OSC is not guaranteed. When power is applied for the first time, the OSC bit should be enabled. When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC registers. This puts the external registers into a static state, allowing the data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted by writing a 1 to the read bit (R). As long as a 1 remains in the R bit, updating is inhibited. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers resume within one second after the R bit is set to 0 for a minimum of 500Fs. The R bit must be 0 for a minimum of 500Fs to ensure the external registers have fully updated. As with a clock read, it is also recommended to halt updates prior to setting new time values. Setting the write bit (W) to 1 halts updates of the external RTC registers 8h-Fh. After setting the W bit to 1, the RTC registers can be loaded with the desired count (day, date, and time) in BCD format. Setting the W bit to 0 then transfers the values written to the internal registers and allows normal clock operation to resume. The alarm settings and control for the device reside within RTC registers 2h-5h. The INTERRUPTS register (6h) contains two alarm-enable bits: alarm flag enable (AE) and alarm in backup-mode enable (ABE). The alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. Alarm mask bits AM[4:1] control the alarm mode (Table 2). Configurations not listed in the table default to the once-per-second mode to notify the user of an incorrect alarm setting.
Reading the Clock
DS3065WP
RTC Read Mode
RTC Write Mode
Setting the Clock
Using the Clock Alarm
Clock Oscillator Mode
Table 2. Alarm Mask Bits
AM4 1 1 1 1 0 AM3 1 1 1 0 0 AM2 1 1 0 0 0 AM1 1 0 0 0 0 Once per second When seconds match When minutes and seconds match When hours, minutes, and seconds match When date, hours, minutes, and seconds match ALARM RATE
11
3.3V, 8Mb, Nonvolatile SRAM with Clock DS3065WP
VTP VCC
ABE, AE
AF
Figure 1. Battery-Backup Mode Alarm Waveforms
When the RTC register values match alarm register settings, the alarm flag (AF) is set to 1. The AE and ABE bits are reset to 0 during the power-up transition, but an alarm generated during power-up sets AF to 1. Therefore, the AF bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. Figure 1 illustrates alarm timing during battery-backup mode and power-up states. The DS3065WP and DS9034I-PCX+ are each individually tested for accuracy. Once mounted together, the module typically keeps time accuracy to within Q1.53 minutes per month (35ppm) at +25NC and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. The electrical environment also affects clock accuracy, and caution should be taken to place the component in the lowest level EMI section of the PCB layout. For additional information, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks (RTCs). Upon each application of power to the device, the following register bits are automatically set to 0: WDS = 0, BMB[4:0] = 0, RB0 = 0, RB1 = 0, AE = 0, ABE = 0. All other RTC bits are undefined.
Clock Accuracy
The device provides full functional capability for VCC greater than 3.0V and write protects by 2.8V. Data is maintained in the absence of VCC without additional support circuitry. The NV SRAM constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write protects itself. All inputs become don't care, and all data outputs become high impedance. As VCC falls below approximately 2.5V (VSW), the powerswitching circuit connects the lithium energy source to the clock and SRAM to maintain time and retain data. During power-up, when VCC rises above VSW, the power-switching circuit connects external VCC to the clock and SRAM and disconnects the lithium energy source. Normal clock or SRAM operation can resume after VCC exceeds VTP for a minimum duration of tREC. When the DS9034I-PCX+ battery cap is first attached to a DS3065WP base, the RTC oscillator is disabled and the lithium battery is electrically disconnected, guaranteeing that no battery capacity has been consumed during transit or storage. When VCC is first applied at a level greater than VTP, the lithium battery is enabled for backup operation. The user is required to enable the oscillator (MSB of the SECONDS register) and initialize the required RTC registers for proper timekeeping operation.
Data-Retention Mode
Freshness Seal
Power-On Default States
12
3.3V, 8Mb, Nonvolatile SRAM with Clock
Table 3. RTC Register Map
ADDR xxxxFh xxxxEh xxxxDh xxxxCh xxxxBh xxxxAh xxxx9h xxxx8h xxxx7h xxxx6h xxxx5h xxxx4h xxxx3h xxxx2h xxxx1h xxxx0h x= X= Y= 0= FT = OSC = W= X X X X X OSC W Y AE AM4 AM3 AM2 AM1 Y WF Y AF R Y Y Y Y X X FT X X 10 HOUR 10 MINUTES 10 SECONDS 10 CENTURY Y ABE 10 DATE 10 HR 10 MINUTES 10 SECONDS Y 0 Y BLF Y 0 Y Y Y Y DATA B7 B6 B5 10 YEAR X 10 MO 10 DATE X X HOUR MINUTES SECONDS CENTURY Y Y DATE HOURS MINUTES SECONDS Y 0 R= AE = ABE = AM[4:1] = WF = AF = BLF = Y 0 Read bit Alarm flag enable Alarm in backup-mode enable Alarm mask bits Watchdog flag Alarm flag Battery-low flag Y 0 Y Y Y Y B4 B3 B2 YEAR MONTH DATE DAY B1 B0 FUNCTION YEAR MONTH DATE DAY HOUR MINUTES SECONDS CONTROL Unused INTERRUPTS ALARM DATE ALARM HOURS ALARM MINUTES ALARM SECONDS Unused FLAGS RANGE 00-99 01-12 01-31 01-07 00-23 00-59 00-59 00-39 -- -- 01-31 00-23 00-59 00-59 -- --
DS3065WP
Don't care address bits Unused; read/writable under write and read bit control Unused; read/writable without write and read bit control Reads as 0 and cannot be changed Frequency test bit Oscillator start/stop bit Write bit
13
3.3V, 8Mb, Nonvolatile SRAM with Clock DS3065WP
CE
VIH tCCS tCCS
VIH
CS
VIH
VIH
Figure 2. SRAM/RTC Data Bus Control
Applications Information
To achieve the best results when using the device, decouple the power supply with a 0.1FF capacitor. Use a high-quality, ceramic, surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
Power-Supply Decoupling
The device can be cleaned using aqueous-based cleaning solutions. No special precautions are needed when cleaning boards containing a DS3065WP module, provided that the cleaning and subsequent drying process is completed prior to the DS9034I-PCX+ attachment. DS3065W modules are recognized by Underwriters Laboratories (UL) under file E99151.
Recommended Cleaning Procedures
Care should be taken to avoid simultaneous access of the SRAM and RTC devices (see Figure 2). Any chipenable overlap violates tCCS and can result in invalid and unpredictable behavior.
Avoiding Data Bus Contention
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 34 PCAP PACKAGE CODE -- OUTLINE NO. 21-0246 LAND PATTERN NO. See the outline no. 21-0246
14
3.3V, 8Mb, Nonvolatile SRAM with Clock
Revision History
REVISION NUMBER 0 REVISION DATE 7/10 Initial release DESCRIPTION PAGES CHANGED --
DS3065WP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
15
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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